Memory elements, such as D flip-flops (DFF), are subject to upset from cosmic neutrons and terrestrial alpha particles, which can result in systematic errors in an integrated circuit device having memory elements. The failure rate associated with these upsets is commonly known as a Soft Error Rate (SER). An industrial metric used to quantify the SER of the circuit is known as Failure In Time (FIT) rate or FIT/Mb. A sensitive area may be an area that can collect charge from energetic particles to cause a soft error, and is usually referred to a reverse-biased drain.
In advanced technology nodes, dummy gates/transistors are often used and/or required by design rules to enable compact layout by maintaining continuity of one or both of a diffusion area and polysilicon gate lines. While the addition of the dummy gate/transistor does not affect the functionality of the FF cell, these dummy gates/transistors at sensitive nodes of the memory devices add up to the overall sensitive areas of the memory devices, and therefore increase the device FIT rate.
Further, memory elements may have an asymmetry with respect to storing a logical “0” or logical “1”, where the asymmetry may be the result of parasitic dummy gates for example. For an integrated circuit produced using a 7 nm FF (i.e. a 7 nm gate width), a 3-5 times FIT asymmetry can be observed between ‘0’ and ‘1’, while another integrated circuit using another 7 nm FF may experience 10-100 times FIT asymmetry between ‘1’ and ‘0’.
Accordingly, there is a need for a memory cell that improves the FIT rate.